Embedded Microphone Equalization for Array Applications
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Master Thesis of Maintz, Thomas
The analysis of a sound field with an array of microphones reveals detailed information about its directional properties. To achieve a high spatial resolution many microphones are required, typically resulting in high costs when using standard electret microphones. To reduce costs, Micro Electro Mechanical System (MEMS) microphones are used. These, however, show a non-ideal frequency response. Thus, the frequency- and phase response of all individual microphones have to be equalized for their application in microphone arrays. The internal logic of Field Programmable Gate Arrays (FPGA) can be customized to implement a live-equalization of microphones. In this thesis the Xilinx Zynq FPGA is choosen for this purpose. In addition to the programmable logic block the Xilinx Zynq platform includes two ARM-processors which connect to the programmable logic block via standardized protocols. These can be used to interface the FPGA logic and program the filter coefficients into the programmable logic. Further, optimized atomic architectures for digital signal processing are provided within the Zynq FPGA. This thesis outlines the conception and implementation of a scalable convolution kernel with minimum latency for the equalization of larger scale microphone arrays in hardware. The implementation is carried out on the Xilinx Zynq FPGA platform relying on pipelining. Parallel FIR- and Biquad-Filters are implemented and can be customized for each microphone channel individually. By applying a hybrid convolution technique with time and frequency domain convolution, the length of the equalization filters can be extended. To reduce the total number of FFT operations the symmetry properties in the spectra of real valued time signals are used. The solution will be used inside a spherical microphone array yielding a live-equalization of the individual microphone signals. Eventually, the output signals are converted to a MADI stream allowing for a standardized interface to a measurement PC. Further, the implementation is analyzed with respect to the limitations of the used fixed-point arithmetic. Finally, results are compared to computational results of a Golden Reference Modell implemented in floating-point arithmetic.